SPI0 status
| RXTH | Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit. |
| TXTH | Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTIMEOUT | Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| BUSERR | Bus Error. When 1, a bus error has occurred while processing data for SPI. The bus error flag can be cleared by writing a 1 to this bit. |
| RXEMPTY | Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit. |
| TXEMPTY | Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXCOUNT | Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field. |
| TXCOUNT | Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled. |